The packaging of semiconductor chips is an important step in the total chip fabrication process. The purposes of packaging is to provide electrical connection, to expand the chip electrode pitch for the next level packaging, to protect the chip from mechanical and environmental stress, and furthermore, to provide a proper thermal path for the heat that the chip dissipates.
One of the more popularly utilized packaging techniques is the plastic package. A plastic package can be produced by an automated injection molding process and can be very cost competitive. In a typical plastic package, a chip is attached to the paddle portion of a lead frame. The lead frame which is made of etched or stamped thin metal of typically iron-nickel or copper alloys, serves as an outer frame around which the package can be assembled. The lead frame further provides external leads in a completed package. Interconnections can be achieved by fine gold wire between the lead fingers and the bond pads on an IC device. A plastic encapsulation process can be carried out in a transfer molding method by utilizing typically an epoxy resin. The epoxy resin encapsulates the IC chip and forms the peripheral shape of the package at the same time. The external leads can be formed into their final shape after the plastic molding process is completed. A typical plastic package therefore is a composite structure consisting of a silicon chip, a metal lead frame and a plastic molding compound. The chip support paddle and the inner tips of the lead fingers are silver plated, while the external leads are solder coated after the molding process is completed.
A more recently developed plastic package for IC chips is the lead-on-chip (LOC) package. In a LOC package, both the lead frame and the bonding wires are positioned on top of the IC circuit. LOC package is used in modern high density memory devices wherein a plurality of lead fingers are disposed on and attached to an active surface of an IC chip. A major benefit provided by the LOC package is that the ratio between the size of the IC chip and the size of the package is significantly higher than conventional packages since the mounting area, i.e., the die pads, is no longer required in a LOC package. The high ratio between the chip size and the package size is very desirable in the ever increasing miniaturization of IC devices. In a LOC package, a metal lead frame substantially covers the active devices of the chip, it is therefore more difficult to perform a failure analysis on the top surface of a LOC package.
In the molding of a plastic package, the flow pattern of a plastic melt in a mold must be carefully controlled in order to produce a quality product. Difficulty arises when an IC chip and a lead frame is positioned in a mold cavity which has a very small gap from the mold surface. The flow channel for the plastic is very small and thus the lay out of the chip/lead frame in relation to the mold must be carefully designed. When the mold flow during a molding process is inadequate, plastic packages containing large voids are produced. These packages must be scrapped when the void content is significant. The void formation in a plastic package not only affects the thermal conductivity of the plastic, but also serves as a moisture trap which collects moisture which is detrimental to both the metal bond pads on the chip and the epoxy packaging material. The void formation in plastic packages are sometimes caused by a poorly designed mold flow pattern which traps air easily on the top or bottom side of the chip.
A conventional plastic package that contains large void formation is shown in FIGS. 1A.about.1D. As shown in FIG. 1A, plastic package 10 is on its bottom side which indicates a large void formation 12 with essentially no plastic coverage. On the top side of the package 10, a large void 14 also present due to a short shot, or trapped air during the molding process. This is shown in FIG. 1B. Another conventional plastic package 10 is shown in FIG. 1C with voids 18 caused by trapped air. FIG. 1D shows a perspective view of a plastic package 10 which has insufficient coverage after a plastic molding process. The plastic package 10 is a lead-on-chip package which consists of a dam-bar 20, lead fingers 22, chip 24 and an outer frame 26. The LOC package 10 shows a large void formation 28 on a top surface 30 and a large void formation 32 on a bottom surface 34. The void formation 28, 32 are mainly caused by trapped air and inadequate flow channel design. It is noted that the plastic flow velocity along the edges 36 of the package is faster than the center of the package and thus causing void formation. The balancing of mold flow for encapsulating a semiconductor chip is therefore an important aspect of the packaging process.
It is therefore an object of the present invention to provide a method for forming a plastic package of an electronic device without the drawbacks and shortcomings of the conventional methods.
It is another object of the present invention to provide a method for forming a plastic package of an electronic device without void formation that can be carried out by the same processing equipment used in conventional methods.
It is a further object of the present invention to provide a method for forming a plastic package of an electronic device without void formation wherein a semiconductor chip and a lead frame are encapsulated in an injection molded plastic material.
It is another further object of the present invention to provide a method for balancing mold flow in encapsulating IC devices by first providing a lead frame and then deforming the lead fingers to improve the flow pattern in the mold.
It is still another object of the present invention to provide a method for balancing mold flow in encapsulating IC devices by first providing a lead frame and then deforming lead fingers of the lead frame such that, after the device and the lead frame are loaded into a mold cavity, a flow channel above the lead frame and a flow channel below the lead frame are substantially the same.
It is yet another object of the present invention to provide a method for balancing mold flow in encapsulating IC devices by utilizing a lead frame wherein the lead fingers are deformed into a U or V-shaped bend for improving plastic flow in the mold.
It is still another further object of the present invention to provide a method for balancing mold flow in encapsulating IC devices by providing a lead frame and then deforming the lead fingers into fingers having sloped planes such that the flow channel can be modified.
It is yet another further object of the present invention to provide a method for balancing mold flow in encapsulating IC devices by first providing a lead frame which has lead fingers that are deformed into V or U-shaped notches to modify the flow pattern in the mold.